MTIA
Meta’s vertically integrated accelerator family for recommendation, ranking and emerging training workloads.
Google TPU
Google’s systolic-array accelerator family, evolving from inference cards to pod-scale AI supercomputers.
NVIDIA Blackwell
A rack-scale computing platform built around dual-die GPUs, HBM3E and fifth-generation NVLink.
High Bandwidth Memory
Stacked DRAM beside the accelerator package, optimized for extreme bandwidth and energy-efficient data movement.
NVLink & NVSwitch
A high-bandwidth coherent GPU fabric that turns many accelerators into one logical compute domain.
Direct-to-Chip Cooling
A facility-to-chip heat-removal chain using cold plates, CDUs and warm-water loops.
800VDC Power
A high-voltage direct-current architecture intended to reduce conversion stages and conductor losses in dense AI facilities.
AI Factory
The complete production chain that converts electricity, silicon and software into useful model output.
Microsoft Maia
Microsoft’s in-house AI accelerator program designed to align Azure models, networking and datacenter deployment.
AWS Trainium
AWS’s training accelerator platform, integrated with Neuron software and Elastic Fabric Adapter networking.
AMD MI300X
A high-memory accelerator using chiplets and HBM to target large-model inference and training.
NVIDIA Rubin
NVIDIA’s post-Blackwell platform direction, combining next-generation compute, memory, networking and rack architecture.
CXL
A cache-coherent interconnect for attaching memory and accelerators while enabling pooling, expansion and composability.
Chiplets
A modular silicon strategy that partitions compute, I/O and memory functions across multiple dies in one package.
CoWoS Packaging
TSMC’s advanced packaging family connecting large compute dies and HBM through silicon interposers and substrates.
Ethernet for AI
The scale-out network architecture increasingly optimized for lossless, high-radix AI clusters.
InfiniBand
A purpose-built high-performance fabric emphasizing low latency, RDMA and mature collective communication.
Co-Packaged Optics
Moving optical engines closer to switch silicon to overcome electrical reach, power and front-panel density limits.
Linear Pluggable Optics
A lower-power optical module architecture that removes the module DSP and relies on host SerDes quality.
Optical Transceivers
Pluggable modules connecting switches and servers across scale-up, scale-out and datacenter interconnect networks.
KV Cache
The persistent attention state that trades memory capacity and bandwidth for lower autoregressive decoding cost.
FlashAttention
An IO-aware attention algorithm that reduces HBM traffic by tiling computation through on-chip memory.
Mixture of Experts
Sparse expert routing increases model capacity while activating only a subset of parameters per token.
Speculative Decoding
A draft-and-verify technique that accelerates autoregressive generation when a smaller model predicts accepted tokens.
GPU Scheduling
Admission, batching, placement and preemption policies that convert expensive accelerators into useful service capacity.
AI Storage
A layered storage system for datasets, checkpoints, model weights and high-throughput inference artifacts.
Gas Turbines for AI
On-site generation used to bridge grid delays, provide resilience or support behind-the-meter AI campuses.
AI Datacenter Substations
High-voltage grid interconnection, transformation, protection and distribution for campuses measured in hundreds of megawatts.
UPS & BESS
Short-duration energy systems that ride through disturbances, support orderly transfer and increasingly participate in grid services.
Cold Plates
Liquid-cooled heat spreaders that move heat from GPU packages into facility water loops.
Cooling Distribution Units
The hydraulic and control boundary between facility water and technology cooling systems.
Water Treatment
Water chemistry, filtration and treatment practices that protect heat exchangers, towers and liquid cooling loops.
AI Rack Architecture
The mechanical, electrical, thermal and network design envelope around dense accelerator systems.
AI Infrastructure TCO
A full-cost model linking hardware, power, cooling, networking, utilization and service life to useful output.
Switch Attachment Rates
A demand model translating accelerator deployments into leaf, spine, NVSwitch, optics and cable content.
AI Datacenter EPC
The engineering, procurement and construction workflow for delivering power-dense AI campuses under severe schedule pressure.
AI Cloud Economics
The unit economics of renting accelerators, balancing utilization, financing, power, software and customer mix.
Inference Economics
The conversion of model architecture and serving policy into latency, tokens per second and cost per request.
Silicon Photonics
Integrated optical components manufactured using semiconductor processes for high-volume datacenter links.
112G & 224G SerDes
High-speed electrical I/O that sets reach, power and equalization requirements across boards, cables and optical modules.